Analysis and Comparison of Harmonic Reduction in Multilevel Inverters

Vol.4 No.1

Year: 2010

Issue: Jul-Sep

Title: Analysis and Comparison of Harmonic Reduction in Multilevel Inverters   

Author Name: Mahesh Manivanna Kumar, Rama Reddy   

Synopsis:   

This paper presents a multilevel inverter with harmonics reduction along with the reduction in number of switches. The reduction in harmonic content in the three-level neutral-point-clamped (NPC), capacitor clamped inverter with inductive load is obtained by simulation. Similarly the reduction in harmonic content in the cascaded multilevel inverter is obtained. The percentage (%) THD is calculated for various levels (3, 7 and 9 level). Finally the percentage (%) THD obtained from various levels is compared. The functionality verification of the multilevel inverter circuit is done using PSPICE and MATLAB. The harmonic reduction is achieved by selecting appropriate switching angles.