A 10-bit Ultra-Low-Power SAR ADC with a Novel DAC Switching Method

Vol.4 No.3

Year: 2011

Issue: Jan-Mar

Title: A 10-bit Ultra-Low-Power SAR ADC with a Novel DAC Switching Method   

Author Name: Weibo Hu, Donald Lie   

Synopsis:   

A 10-bit single-ended ultra-low-power Successive Approximation Register ADC with a novel DAC switching technique is designed in the TSMC 0.18µm mixed-signal CMOS technology. This method uses a reference voltage of VR/2, rather than VR, as the only reference voltage to digitize the input signals with the amplitude range of [0, VR]. Compared with the conventional switching method, this work reduces the size of binary-weighted capacitor array by 50%, lowering the average power consumption in the DAC during digitizing by 87.5%, and it also reduces the power consumption during sampling by 63.5%. With the sampling frequency of 77 kHz, ADC’s post-layout simulation resolution is 8.84 bits and ERBW (Effective Resolution Bandwidth) is 60 kHz, and the post-layout simulation FOM of our 10-bit SAR ADC can reach 18.9 fJ/(conversion-step), which is among the best ADCs FOM reported in a CMOS 0.18 µm technology.